★ CRIMSPIRE LLC — INDIANAPOLIS, IN     ◆ RISC-V EMBEDDED SYSTEMS     ★ HARTPROBE NOW IN DEVELOPMENT     ◆ OPEN SOURCE · OPEN HARDWARE     ★ CRIMSPIRE LLC — INDIANAPOLIS, IN     ◆ JOIN THE RISC-V REVOLUTION
EST. 2024 — INDIANAPOLIS, IN — RISC-V DIVISION

BUILD ON
RISC‑V

Open Hardware · Open Source · Open Future

Crimspire builds the tooling, compute boards, and modules that the RISC-V ecosystem is missing. From debug probes to certified SoMs — we make RISC-V real for engineers and builders.

View Products GitHub ↗
3
Products in Roadmap
100%
Open Source Firmware
RISC-V
Architecture
$45
HartProbe Starting Price

The Hart Series

Three products. One mission. Filling the tooling, compute, and module gaps holding RISC-V back.

02
Coming Soon
HartBoard
RISC-V Robotics Compute Board

A RISC-V compute board built for robotics and industrial use. CAN bus, real-time I/O, and ROS2 support — everything missing from existing RISC-V SBCs.

  • RISC-V SoC with real-time core
  • CAN bus (ISO 11898)
  • ROS2 ready, micro-ROS support
  • Industrial I/O headers
  • Designed for harsh environments
03
Roadmap
HartModule
Certified RISC-V System-on-Module

A production-ready, certified RISC-V SoM for builders who want to ship products — not prototype forever. FCC/CE certified, drop-in compute for your next product.

  • FCC / CE pre-certified
  • castellated / LCC mounting
  • Production-tested supply chain
  • Long-term availability commitment
  • Carrier board reference design
System Status

Built in Public

Every line of HartProbe firmware is open source. Schematics, configs, and OpenOCD profiles — all on GitHub. The RISC-V community deserves open tooling.

[FW]
Firmware

MIT licensed STM32 firmware, auditable and forkable.

[HW]
Hardware

KiCad schematics and PCB files released openly.

[CFG]
Configs

Per-board OpenOCD configs for every supported target.

[DOC]
Docs

Full documentation, wiring guides, and examples.

hartprobe — openocd session
$ openocd -f hartprobe.cfg -f milkv-duo.cfg
Open On-Chip Debugger 0.12.0
Info : HartProbe v1.0 found
Info : JTAG tap: riscv.cpu tap/device
Info : Hart 0 — HALTED
Info : Listening on port 3333 for gdb

$ riscv32-unknown-elf-gdb firmware.elf
(gdb) target remote :3333
Remote debugging using :3333
(gdb) load
Loading section .text, done.
(gdb)

Who We Are

Crimspire LLC is an embedded systems company based in Indianapolis, Indiana. We exist because the RISC-V ecosystem deserves better tooling — and nobody was building it.

We're starting with HartProbe: a debug probe that actually works with your RISC-V board, out of the box, without a forum post and a spare STM32. Then HartBoard, then HartModule — building the connective tissue the RISC-V ecosystem needs to go from hobbyist curiosity to production platform.

We build in public. Open source firmware, open hardware, community first.

Stay in the Loop

HartProbe is in active development. Follow along on GitHub or reach out directly.